// D import file generated from '../../../../libphobos/libdruntime/core/cpuid.d'
module core.cpuid;
@trusted nothrow 
{
	version (D_InlineAsm_X86)
	{
		version = InlineAsm_X86_Any;
	}
	else
	{
		version (D_InlineAsm_X86_64)
		{
			version = InlineAsm_X86_Any;
		}
	}
	public 
	{
		struct CacheInfo
		{
			size_t size;
			ubyte associativity;
			uint lineSize;
		}
		public 
		{
			__gshared CacheInfo[5] datacache;

			@property 
			{
				const(CacheInfo)[5] dataCaches();
				string vendor();
				string processor();
				bool x87onChip();
				bool mmx();
				bool sse();
				bool sse2();
				bool sse3();
				bool ssse3();
				bool sse41();
				bool sse42();
				bool sse4a();
				bool aes();
				bool hasPclmulqdq();
				bool hasRdrand();
				bool avx();
				bool vaes();
				bool hasVpclmulqdq();
				bool fma();
				bool fp16c();
				bool avx2();
				bool hle();
				bool rtm();
				bool amd3dnow();
				bool amd3dnowExt();
				bool amdMmx();
				bool hasFxsr();
				bool hasCmov();
				bool hasRdtsc();
				bool hasCmpxchg8b();
				bool hasCmpxchg16b();
				bool hasSysEnterSysExit();
				bool has3dnowPrefetch();
				bool hasLahfSahf();
				bool hasPopcnt();
				bool hasLzcnt();
				bool isX86_64();
				bool isItanium();
				bool hyperThreading();
				uint threadsPerCPU();
				uint coresPerCPU();
				bool preferAthlon();
				bool preferPentium4();
				bool preferPentium1();
			}
			__gshared public 
			{
				uint stepping;
				uint model;
				uint family;
				uint numCacheLevels = 1;
				@property uint cacheLevels();

				private 
				{
					bool probablyIntel;
					bool probablyAMD;
					string processorName;
					char[12] vendorID;
					char[48] processorNameBuffer;
					uint features = 0;
					uint miscfeatures = 0;
					uint extfeatures = 0;
					uint amdfeatures = 0;
					uint amdmiscfeatures = 0;
					ulong xfeatures = 0;
					uint maxCores = 1;
					uint maxThreads = 1;
					@property bool hyperThreadingBit();

					enum : uint
					{
						FPU_BIT = 1,
						TIMESTAMP_BIT = 1 << 4,
						MDSR_BIT = 1 << 5,
						CMPXCHG8B_BIT = 1 << 8,
						SYSENTERSYSEXIT_BIT = 1 << 11,
						CMOV_BIT = 1 << 15,
						MMX_BIT = 1 << 23,
						FXSR_BIT = 1 << 24,
						SSE_BIT = 1 << 25,
						SSE2_BIT = 1 << 26,
						HTT_BIT = 1 << 28,
						IA64_BIT = 1 << 30,
					}
					enum : uint
					{
						SSE3_BIT = 1,
						PCLMULQDQ_BIT = 1 << 1,
						MWAIT_BIT = 1 << 3,
						SSSE3_BIT = 1 << 9,
						FMA_BIT = 1 << 12,
						CMPXCHG16B_BIT = 1 << 13,
						SSE41_BIT = 1 << 19,
						SSE42_BIT = 1 << 20,
						POPCNT_BIT = 1 << 23,
						AES_BIT = 1 << 25,
						OSXSAVE_BIT = 1 << 27,
						AVX_BIT = 1 << 28,
						FP16C_BIT = 1 << 29,
						RDRAND_BIT = 1 << 30,
					}
					enum : uint
					{
						FSGSBASE_BIT = 1 << 1,
						BMI1_BIT = 1 << 4,
						HLE_BIT = 1 << 5,
						AVX2_BIT = 1 << 6,
						SMEP_BIT = 1 << 8,
						BMI2_BIT = 1 << 9,
						ERMS_BIT = 1 << 10,
						INVPCID_BIT = 1 << 11,
						RTM_BIT = 1 << 12,
					}
					enum : ulong
					{
						XF_FP_BIT = 1,
						XF_SSE_BIT = 2,
						XF_YMM_BIT = 4,
					}
					enum : uint
					{
						AMD_MMX_BIT = 1 << 22,
						FFXSR_BIT = 1 << 25,
						PAGE1GB_BIT = 1 << 26,
						RDTSCP_BIT = 1 << 27,
						AMD64_BIT = 1 << 29,
						AMD_3DNOW_EXT_BIT = 1 << 30,
						AMD_3DNOW_BIT = 1 << 31,
					}
					enum : uint
					{
						LAHFSAHF_BIT = 1,
						LZCNT_BIT = 1 << 5,
						SSE4A_BIT = 1 << 6,
						AMD_3DNOW_PREFETCH_BIT = 1 << 8,
					}
					version (InlineAsm_X86_Any)
					{
						__gshared 
						{
							uint max_cpuid;
							uint max_extended_cpuid;
						}
						void getcacheinfoCPUID2();
						void getcacheinfoCPUID4();
						void getAMDcacheinfo();
						void getCpuInfo0B();
						void cpuidX86();
						bool hasCPUID();
					}
					else
					{
						bool hasCPUID();
						void cpuidX86();
					}
					shared static this();
				}
			}

		}
	}
}

